underfl0w wrote:Since both support DDR4 at roughly the same frequencies, will the new DMI 3 bus actually see the benefits of its double link speed from DMI 2 in X99 systems? (Either of them seem like a step backward compared to QPI's theoretical bandwidth capabilities though.)
For anything that is using the DMI interface, probably. Is your memory controller using it (the DMI) to talk to the RAM. No. The memory controller communicates directly to the RAM at the frequency set, via DDR4 signalling.
From a Sandy Bridge onwards, consumer processors use derivative of the QPI for the internal interconnect ring, although the data bus was only 32bits wide, rather than the 64bits of the QPI (not sure if this has increased in newer architectures).
QPI is only listed on the 5820K because it is part of the Xeon family so it is using QPI as the internal interconnect ring, rather than the unnamed interconnect that is used in consumer processors. The interconnect is presumably publicly unnamed, because it is not externally exposed. There is no external exposure of the QPI on a 5820K either; it is used internally.
The speed of the interconnect does not automatically affect your memory bandwidth, which is limited by the memory controller, it's clock, and your RAM. It does affect how fast the memory controller communicates with other participants on the interconnect.
DMI3 will definitely matter when communicating with the South Bridge (which is done via the memory controller). A 5820K has DMI2. Would you actually notice a difference between DMI2 and DMI3. Only if you managed to flood the South Bridge. Maybe a SSD RAID would do it..
edit: clarified a couple of specifics.